The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to interconnect structures and methods for forming an interconnect structure.
An interconnect structure may be used to electrically connect device structures fabricated by front-end-of-line (FEOL) processing. A back-end-of-line (BEOL) portion of the interconnect structure may include metallization formed using a damascene process in which via openings and trenches etching in a dielectric layer are filled with metal to create features of a metallization level. The dielectric layer may be formed from low-k dielectric materials that provide a reduced capacitance, but such reduced-capacitance dielectric layers are also required to provide a high level of reliability.
Improved interconnect structures and methods for forming an interconnect structure are needed.